# Talk:CPU Frequency

Could someone explain this?

I didn't find any explanation in the docs (MMSP2 Databook v1.0). Did anybody measure the resulting frequency?

The question restated using C code (mm points to 0xc0000000):

unsigned cpuHz920() {

``` /* Crystal input p.31 */
const unsigned XTI=7372800;
uint16_t *mm16=(unsigned short *)mm;
/* p.108 FCLK PLL Value Setting Register
PLL = phase-locked loop?
http://en.wikipedia.org/wiki/PLL
*/
uint16_t FPLLVSETREG=mm16[0x912>>1];
/* p.109
[15:8] mdiv of pll */
uint8_t FMDIVR= (FPLLVSETREG & 0xff00) >> 8;
DEBUG(FMDIVR);
/* [7:2] pdiv of pll */
uint8_t FPDIVR = (FPLLVSETREG & 0xfc) >> 2;
DEBUG(FPDIVR);
/* [1:0] sdiv of pll */
uint8_t FSDIVR = FPLLVSETREG & 3;
DEBUG(FSDIVR);
```
``` /* p. 88, 109
System clock set register
*/
uint16_t SYSCSETREG=mm16[0x91c>>1];
```
``` /* [8:6] DCLK Clock Generation F-PLL Divide Set Value (N-1)
DCLK means Double Clock, it is used for the memory controller
so, BCLK is DCLK*1/2 */
uint8_t DCLKDIV = (SYSCSETREG & 0x1c0) >> 6;
DEBUG(DCLKDIV);
/* [5:3] A940T FCLK Clock Generation F-PLL Divide Set Value (N-1) */
uint8_t A940TFDIV = (SYSCSETREG & 0x38) >> 3;
DEBUG(A940TFDIV);
/* [2:0] A920T FCLK Clock Generation F-PLL Divide Set Value (N-1) */
uint8_t A920TFDIV = SYSCSETREG & 7;
DEBUG(A920TFDIV);
```
``` /* why? perhaps p.85? */
unsigned FCLKin = (XTI * (((unsigned)FMDIVR) + 8))
/((((unsigned)FPDIVR) + 2) << FSDIVR);
return FCLKin / (((unsigned)A920TFDIV)+1);
```

}

The FCLKin line is the one I couldn't verify in the docs.